Analog Circuits for GATE ECE 2027: Important Topics

Analog Circuits averaged 10.8 marks across the five GATE EC papers counted question by question for this site (2010, 2019, 2020, 2025 and 2026). That puts it third in the paper, behind Networks, Signals and Systems and Engineering Mathematics. It is also the section that has grown: 9 marks in 2010 and 2019, then 11, 13 and 12.

The marks here are rarely lost on algebra. They are lost on a decision made before any algebra: which diode is conducting, whether the transistor is in the active region, whether the op-amp has negative feedback. This guide sets out what the counted papers asked, what they never asked, and what the 2027 syllabus added.

Key takeaways

• 34 questions and 54 marks across five papers, 14 of them 1-mark and 20 of them 2-mark.
• Three families appear in four of five papers: ideal-diode networks, BJT small-signal amplifiers, and op-amp circuits by the virtual short. Together with MOSFET small-signal work they account for 31 of the 54 marks.
• DC biasing was absent from 2010, 2019 and 2020, then appeared in both 2025 and 2026.
• Oscillators, dominant-pole (Miller) compensation and phase margin have zero counted questions. The last two are new to the 2027 syllabus.
• The 2019 paper, set by IIT Madras which also sets GATE 2027, had no op-amp question, no BJT question, and four numerical-answer questions out of five.
• Question numbers follow the book's count, which runs 1 to 65 through each paper. The 2019 and 2020 papers restart their technical questions at 1, so subtract 10 to find them there.

What the section is worth

Only 55.9 per cent of the counted questions were multiple choice, one of the lowest shares in the paper. More than a third were numerical answers, where there is nothing to eliminate and the number has to be produced. All three multiple-select questions came from one paper, 2025.

Grouped by the syllabus's own three sentences, BJT and MOSFET amplifiers took 24 marks, diode circuits including Zener regulation 16, and op-amp circuits 14. For how this compares with the other sections, see the GATE ECE subject-wise weightage guide.

The circuits that recur

Diode networks are the most reliable question in the section. The circuit changes every year and the asked quantity rotates: an average value (2019 Q.34), a voltage doubler's output (2020 Q.27), a transfer characteristic (2025 Q.57), a conduction interval (2025 Q.61), a maximum output (2026 Q.65). The skill never changes. Decide the state of each diode in each region of the input, then do simple arithmetic.

Small-signal questions usually hand you the transconductance. The mark is for knowing which formula the topology calls for, not for deriving it. As an illustration of our own: a BJT biased at 1 mA with a thermal voltage of 25 mV has a transconductance of 40 mA/V, and a common-emitter stage with a 5 kΩ collector load then has a midband gain of about $-200$:

The traps are the unbypassed emitter resistor, which degenerates the gain, and the factor of 2 between single-ended and differential outputs.

The op-amp question is usually the quickest mark in the section. Apply the virtual short and report one voltage or current. 2026 alone asked three (Q.17, Q.53 and Q.62, worth 5 marks), the most any counted paper spent on op-amps.

Zener regulators prepare two sections at once. 2019 Q.48 and 2025 Q.47 could equally be counted under Electronic Devices. All three regulator questions were 2-mark, and each came down to little more than one KCL at the reference node.

Biasing has returned. Zero marks in the three earlier papers, then 1 mark in 2025 and 3 in 2026. It is one loop equation for the setter, which makes it a natural 1-mark item.

What five papers never asked

• Oscillators. Named in the syllabus beside the Schmitt trigger, and not one counted question across four organising institutes.
• Dominant-pole (Miller) compensation and phase margin. Both are new syllabus text for 2027, so the absence is expected.
• Anything outside the three syllabus sentences. The syllabus does not name power amplifiers, 555 timers or log and antilog amplifiers, and all 34 counted questions stayed inside its wording.

Frequency response is thin too: one counted question, 2010 Q.49, plus AC coupling embedded in 2026 Q.50.

The 2019 paper and what it suggests

GATE 2027 is set by IIT Madras, and 2019 is the one counted paper IIT Madras also set. Its five analog questions were a diode network on a square wave (Q.34), a Zener shunt regulator (Q.48), a resistor-diode-capacitor transient (Q.62), a CMOS amplifier with an active load (Q.64) and a MOS differential pair with a current-mirror bias (Q.65).

Three things stand out. There was no op-amp question, when every other counted paper had at least one. There was no BJT question; both amplifier items were MOS. And four of the five were numerical answers, the only counted paper where numerical questions outnumbered multiple choice in this section.

One paper is a signal, not a law, and one paper cannot outvote four. The reasonable reading is not to thin out op-amps. It is to make the MOS side as automatic as the BJT side, and to be able to produce a number, not pick an option, for a small-signal gain, an output resistance and a differential-pair current.

What the 2027 syllabus changed

The op-amp sentence now ends with dominant-pole (Miller) compensation, phase margin. The only other difference, "Schmitt triggers" becoming "Schmitt trigger", changes nothing. The full comparison is in the GATE ECE 2027 syllabus changes guide.

Neither addition has a counted precedent, so anything said about how they will be asked is judgement. The nearest anchor is the pair of questions that asked for a $-3$ dB frequency of an op-amp filter, 2020 Q.51 and 2025 Q.34. The natural extensions are the gain-bandwidth product, the closed-loop bandwidth it gives at a stated gain, the Miller multiplication of a feedback capacitance, and phase margin read from the loop gain. Phase margin as a concept was already examinable under Control Systems; what is new is applying it to an op-amp. The syllabus can be revised, so confirm the current PDF on the official GATE 2027 site.

How to prepare it

1. Diode state reasoning, swept across the input range, until the conducting diode is obvious at a glance.
2. Transconductance and the four single-stage formulas, common-emitter or common-source, follower, and common-base or common-gate, for BJT and MOSFET equally.
3. The virtual short, including T-networks in the feedback path and the current an op-amp sources into a load.
4. Zener-referenced regulators: output voltage as the Zener voltage minus the base-emitter drop, $V_o = V_Z - V_{BE}$, then one KCL.
5. DC biasing, including the MOSFET square law with its two roots, only one of which is physical.
6. Current mirrors and differential pairs.
7. Active filters and the Schmitt trigger, then the two 2027 additions as cover.

Practise to a number. Twelve of the 34 counted questions were numerical, including four of the five in 2019, so work examples through on the on-screen calculator rather than stopping at the method. A wrong multiple-choice answer costs $\displaystyle \frac{1}{3}$ mark on a 1-mark question and $\displaystyle \frac{2}{3}$ mark on a 2-mark one; numerical and multiple-select questions carry no negative marking.

For where Analog Circuits sits in a full plan, the GATE ECE important topics guide ranks the recurring concepts across every section. The GATE ECE 2027 book gives the analog chapter 35 questions written for the book, each with a full worked solution, and builds every wrong option from one named mistake. It is part of 925 questions and 10 full mock tests across 814 pages.